为了解决信号斜率对逻辑门延时的影响,提出一种基于逻辑努力的非线性逻辑门延时模型。模型引入非线性修正因子,该修正因子通过对仿真数据的模拟,由优化算法求得。针对不同的连线负载,提出模型得到的延时与仿真得到的延时误差小于3%。仿真结果表明,在不同的连线负载下,采用该模型优化设计的译码器延时最小,验证了模型的有效性。 In order to solve the influence of signal slope on logic gate delay, a logic-based nonlinear logic gate delay model is proposed. The model introduces a non-linear correction factor, which is obtained from the optimization algorithm by simulating the simulation data. According to the different connection load, the delay error of the proposed model is less than 3%. The simulation results show that the decoder designed with this model has the least delay under different connection loads, which verifies the validity of the model.