论文部分内容阅读
设计了一种用于1～4GHz射频前端的全集成CMOS宽带低噪声放大器。利用电流复用技术,对典型并联共栅-共源噪声抵消结构进行改进,以缓和噪声、增益及功耗之间的矛盾。采用在输入端引入电容电感并与MOS管寄生电容构成П形网络的方式来改善输入匹配特性。基于TSMC 0.18μm CMOS工艺进行设计和仿真。仿真结果表明,LNA噪声系数小于3.24dB,输入反射系数S11小于-8.86dB,增益大于15.6dB,IIP3优于+1.55dBm,在1.8V单电源供电条件下功耗仅为16.2mW。
A fully integrated CMOS broadband low noise amplifier designed for 1 ~ 4GHz RF front end is designed. The use of current multiplexing technology, the typical parallel common gate - common source noise cancellation structure to improve, to ease the noise, gain and power consumption of the conflict. The input matching characteristics are improved by introducing capacitive inductance at the input end and forming a Π-shaped network with the MOS tube parasitic capacitance. Design and Simulation Based on TSMC 0.18μm CMOS Process. The simulation results show that the noise figure of LNA is less than 3.24dB, the input reflection coefficient S11 is less than -8.86dB, the gain is more than 15.6dB, IIP3 is better than + 1.55dBm, and the power consumption is only 16.2mW under 1.8V single power supply.