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本文提出了把大家熟悉的ＬＯＣＯＳ（Ｓｉ的局部氧化）技术扩展到ＳｉＣ的可行性。为得到一种ＳｉＣ器件集成的最佳化等平面隔离技术，已在结构上鉴定了两种隔离工艺。第一种是利用ＳｉＣ和Ｓｉ３Ｎ４间不同氧化速率的一般ＬＯＣＯＳ工艺的扩展。第二种方法是＂多场＂工艺，它利用ＳｉＣ上多晶硅氧化的可选择性来形成隔离场区。从扫描电镜图可看到在有源区边界周围有典型的鸟喙图象，对于ＬＯＣＯＳ工艺，它的每边宽为０．９２μｍ（场氧化层等于３０００），而对于＂多场＂工艺，它的每边宽为０．５５μｍ（场氧化层等于８０００）；与一般用于ＳｉＣ的台面式隔离相比，新的技术提高了结构的平整性，允许用于相邻器件间隔离的自对准场阈注入。
This paper presents the feasibility of extending the familiar LOCOS (Local Oxidation of Si) technology to SiC. To obtain an optimized planar isolating technique for integrated SiC devices, two isolation processes have been structurally identified. The first is an extension of the general LOCOS process that utilizes the different oxidation rates between SiC and Si3N4. The second method is a “multi-field” process that utilizes the selectivity of polysilicon oxidation on SiC to form the isolation field. From the scanning electron micrograph, it can be seen that there is a typical beak image around the boundary of the active area, which is 0.92 μm wide on each side (field oxide equals 3000) for the LOCOS process, whereas for the “multi-field” It has a width of 0.55μm on each side (field oxide equal to 8000). Compared with the common mesa for SiC, the new technology improves the flatness of the structure, allowing self-aligning for isolation between adjacent devices Quasi-threshold injection.