用数值计算方法详细模拟了室温及低温(77K)下VLSI电路中金属互连线的寄生电容和时间延迟,得到了金属互连线的几何结构对寄生效应的影响。结果表明,互连线宽W同互连线节距P之比为0.5～0.6是获得最小时间延迟的最佳尺寸。模拟还给出了用铜代替铝金属线及用低介电常数电介质(εlow-k=0.5εSiO2)代替SiO2后,在室温和低温条件下寄生电容及延迟的改善情况 The parasitic capacitance and time delay of metal interconnects in VLSI circuits at room temperature and low temperature (77K) are simulated in detail by numerical methods. The influence of the geometry of metal interconnects on the parasitics is obtained. The results show that the optimal interconnect size P is 0.5 ~ 0.6, which is the best one to get the minimum time delay. The simulation also shows the improvement of the parasitic capacitance and the delay at room temperature and low temperature after substituting copper with aluminum metal wire and using low dielectric constant dielectric (εlow-k = 0.5εSiO2) instead of SiO2