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本文介绍高速低功耗ECL系列中的一组逻辑电路。 该电路系统,由于采用低压电源(—V_(EE)=—3.3伏)供电,明显地降低了电路功耗,由于适当地运用电路技巧,仅用较少的元件就能完成给定的逻辑功能。本电路采用低压恒压源作为恒流偏置,使电路具有较强的适应电源和温度变化的能力。恒压源温度系数小于0.1毫伏/度,电压稳定度典型值为5毫伏/伏。基本门电路输入、输出电平与ECL-10K兼容,其功耗为15毫瓦,平均传播延迟时间t_(pd)=1.5毫微秒。采用肖特基二极管与ECL相結合的半加器,t_(pd)=2.5毫微秒,功耗为16毫瓦。采用先行输出D型触发器,t_(pd)=2毫微秒,功耗为57毫瓦。 全部电路采用常规p-n结隔离工艺。
This article describes a set of logic in the high-speed, low-power ECL family. The circuit system, which uses a low-voltage power supply (-V_ (EE) = -3.3 V), significantly reduces the power consumption of the circuit. Due to the proper use of circuit techniques, a given logic function can be accomplished with fewer components . The circuit uses low-voltage constant-voltage source as constant current bias, the circuit has a strong ability to adapt to changes in power and temperature. The temperature coefficient of the constant voltage source is less than 0.1 millivolts / degree, and the voltage stability is typically 5 millivolts / volt. The basic gate input and output levels are ECL-10K compatible with a power dissipation of 15 milliwatts and an average propagation delay of t_ (pd) = 1.5 ns. Half-adders using a Schottky diode in combination with an ECL, t pd = 2.5 ns, consumes 16 milliwatts. Using the first output D-type flip-flop, t_ (pd) = 2 ns, power consumption is 57 milliwatts. All circuits using conventional p-n junction isolation process.