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论述了一种新近发展的等平面集成注入逻辑(I~8L)技术。这里着重探讨有关采用各种工艺改革并结合拓扑学变化设计来实现高封装密度和优良性能问题。分析了影响I~2L封装密度、直流特性及功率—延迟乘积的因素,提出了设计新结构的若干考虑。并提供了模拟计算、器件参量测量结果及功率—延迟。在100微安注入电流下得到下述门特性:所有的四个收集极β_u≈2—4,四端扇出速度<10毫微秒,单扇出速度<5毫微秒。低电流下速度—功率乘积为0.1微微焦耳。包括互连和电源母线在内实现了封装密度大于300门/毫米~2。
Discussed a newly developed equal-planar integrated injection logic (I ~ 8L) technology. Here focused on the use of a variety of process innovation and design changes in combination with topology to achieve high packaging density and excellent performance issues. The factors influencing I ~ 2L package density, DC characteristics and power - delay products are analyzed, and some considerations for designing a new structure are proposed. It provides simulation calculations, measurement results of device parameters, and power-delay. The following gate characteristics are obtained at a 100 microampere injection current: all four collectors are β_u≈2-4, the fan speed at the four ends is <10 nanoseconds, and the speed of the single fanout is <5 nanoseconds. Speed - Power Product at 0.1 μJ Jitter at Low Current. Including the interconnection and power bus, including packaging density achieved more than 300 / mm ~ 2.