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提出了基于冗余子级的流水线ADC后端校准技术,采用精度较高的流水线冗余子级代替参考ADC,对流水线ADC的各个子级校准,替代了对整个ADC的校准,使校准系统无需降频同步,较好地解决了传统校准系统中主信号通路与参考ADC信号通路不同步的问题。对Matlab/Simulink中搭建的精度为16位、采样频率为10 MS/s的流水线ADC进行仿真,结果表明,当输入信号频率为4.760 5 MHz时,经过校准,流水线ADC的有效位和无杂散动态范围分别由9.37位和59.96dB提高到15.32位和99.55dB。进一步的FPGA硬件验证结果表明,流水线ADC的有效位和无杂散动态范围分别为12.73位和98.62dB,初步验证了该校准算法的可行性。
A redundant sub-stage pipeline ADC back-end calibration technique is proposed. Instead of using a reference ADC, a more accurate pipeline redundancy sub-stage instead of a reference ADC is used to calibrate each sub-stage of the pipeline ADC, instead of calibrating the entire ADC, Frequency synchronization, better solve the traditional calibration system, the main signal path and the reference ADC signal path is not synchronized. The simulation results of a pipeline ADC with 16-bit precision and 10 MS / s sampling rate in Matlab / Simulink show that when the input signal frequency is 4.760 5 MHz, after calibration, the effective bits of the pipeline ADC and no spurs Dynamic range from 9.37 and 59.96dB increased to 15.32 and 99.55dB. Further FPGA hardware verification results show that the effective bits and spurious-free dynamic range of the pipeline ADC are 12.73 bits and 98.62 dB respectively, which proves the feasibility of the calibration algorithm.