论文部分内容阅读
设计了一种精度可编程的低功耗逐次逼近型模数转换器(SAR ADC)。采用电阻电容混合结构的数模转换(DAC)阵列,通过对低位电阻阵列的编程控制,实现了12,10,8位的转换精度,对应不同的精度,电路支持1,5,10 MS/s的转换速率。采用一种改进的单调开关控制逻辑以降低功耗和面积,同时避免了原有单调开关逻辑存在信号馈通的缺点。根据不同的精度要求,对比较器所用预放大器的个数进行编程控制,进一步提高了ADC的功耗效率。电路基于0.18μm的CMOS工艺设计,在1.8V电源电压下,精度从高到低对应的功耗分别为0.56,0.48,0.42mW;SNDR分别为73.2,61.3,48.2dB;SFDR分别为96.3,84.6,62.8dB。芯片内核面积仅为(0.6×0.9)mm~2,适用于通用片上系统(SoC)。
A precision programmable low power successive approximation analog-to-digital converter (SAR ADC) is designed. Adopt the array structure of resistance and capacitance mixed digital-to-analog (DAC) to realize the conversion precision of 12, 10, and 8 bits through the programming control of low resistance array, corresponding to different precision, the circuit supports 1,5,10 MS / s Conversion rate. An improved monotonic switch control logic is used to reduce power consumption and area while avoiding the drawback of signal feedthrough in the original monotonic switch logic. According to different precision requirements, the number of preamplifiers used in the comparator is programmed and controlled, thereby further improving the power consumption efficiency of the ADC. The circuit is based on a 0.18μm CMOS process design. The power consumption from high to low is 0.56, 0.48 and 0.42mW respectively under the 1.8V supply voltage; the SNDR is 73.2, 61.3 and 48.2dB respectively; the SFDR is 96.3 and 84.6 , 62.8dB. The core area of the chip is only (0.6 × 0.9) mm ~ 2, suitable for common system-on-chip (SoC).