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提出一种具有埋层低掺杂漏(BLD)SOI高压器件新结构。其机理是埋层附加电场调制耐压层电场,使漂移区电荷共享效应增强,降低沟道边缘电场,在漂移区中部产生新的电场峰。埋层电中性作用增加漂移区优化掺杂浓度,导通电阻降低;低掺杂漏区在漏极附近形成缓冲层,改善漏极击穿特性。借助二维半导体仿真器MEDICI,研究漂移区浓度和厚度对击穿电压的影响,获得改善击穿电压和导通电阻折中关系的途径。在器件参数优化理论的指导下,成功研制了700V的SOI高压器件。结果表明:BLD SOI结构击穿电压由均匀漂移区器件的204V提高到275V,比导通电阻下降25%。
A new structure of high voltage device with buried low doped drain (BLD) SOI is proposed. The mechanism is that an electric field is added to the buried layer to modulate the electric field of the voltage withstand layer, so that the charge sharing effect in the drift region is enhanced, the electric field at the edge of the channel is lowered, and a new electric field peak is generated in the middle of the drift region. The neutral charge of the buried layer increases the doping concentration in the drift region and decreases the on-resistance. The buffer layer is formed near the drain in the low-doped drain region to improve the drain breakdown characteristics. With the aid of MEDICI, a two-dimensional semiconductor simulator, the effect of concentration and thickness of drift region on the breakdown voltage is studied, and the way to improve the relationship between breakdown voltage and on-resistance is obtained. Under the guidance of the device parameter optimization theory, a 700V SOI high voltage device has been successfully developed. The results show that the breakdown voltage of BLD SOI structure is increased from 204V to 275V in a uniform drift region, which is 25% lower than the on-resistance.