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为了优化片上网络的性能和实现面积,基于环状和蜘蛛网状的拓扑结构和片上网络局部化自相似数据源,分析了虚通道数目和时钟比率对片上网络延迟和吞吐量性能的影响;并在可编程器件EP2S180F1508C5上实现了支持全局异步局部同步结构和虫孔交换的路由节点,分析了虚通道数目对路由节点面积的影响。仿真结果表明:在片上网络局部化自相似数据源下,为了使片上网络达到较高的吞吐量和较低的传输延迟并占用较少的硅片面积,路由节点必须设置3个虚通道和至少2¨1的时钟比率。
In order to optimize the performance and area of the on-chip network, the influence of the number of virtual channels and clock rate on the latency and throughput performance of the on-chip network is analyzed based on the ring-shaped and spider mesh topology and the local self-similar data source of the on-chip network. In EP2S180F1508C5, a routing node supporting global asynchronous local synchronization structure and wormhole switching is implemented, and the influence of the number of virtual channels on the area of routing nodes is analyzed. Simulation results show that in order to make the on-chip network achieve higher throughput and lower transmission delay and occupy less silicon area under the local self-similar data source of the on-chip network, the routing node must set up 3 virtual channels and at least 2 ¨ 1 clock rate.