为满足基于整数小波变换(IWT)的高速图像实时处理系统要求,根据提升小波的框架结构,提出一种基于FPGA多级二维整数小波变换核的结构设计与实现方案。该结构通过将边界扩展过程内嵌于变换过程中,且只需要三行数据缓存,即可以实现行和列同时进行滤波变换。整个变换过程插入多级流水线寄存器,进而降低了功耗,减少了所需内存,达到了更高的处理速度和硬件资源利用率。模块采用VHDL语言进行设计,通过在XCVP30FPGA上验证,该IP核能稳定在100MHz时钟频率下,对尺寸大小为1 600×1 200,深度为12bit图像,当二幅图像输出时间间隔大于图像三行数据输出时间,在不需要将图像分割成小块情况下,就可以同步完成对图像的多级IWT,完全满足高速图像实时处理系统需求。 In order to meet the requirement of high speed image real-time processing system based on integer wavelet transform (IWT), according to the frame structure of lifting wavelet, a design and implementation scheme of multi-level two-dimensional integer wavelet kernel based on FPGA is proposed. The structure of the boundary expansion process embedded in the transformation process, and only three rows of data cache, which can be achieved at the same time row and column filter transformation. The entire conversion process into multi-stage pipeline register, thereby reducing power consumption, reducing the memory required to achieve a higher processing speed and utilization of hardware resources. The module is designed in VHDL and verified by XCVP30FPGA. The IP core can be stabilized at 100MHz clock frequency. For a size of 1 600 × 1 200 and a depth of 12 bit, when the two image output intervals are greater than three lines of data Output time, without the need to split the image into small pieces, you can simultaneously complete the image of the multi-stage IWT, fully meet the needs of high-speed real-time image processing system.