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文中给出了各种最小和算法相关的LDPC码解码算法和它们的并行实现中校验节点更新的典型硬件结构。对于归一化MS的一个校验节点更新,如果当前行的权重是dc,则需要dc次乘,因此,如果dc很大,必然导致高的复杂度。提出一种新的校验节点更新方法,对于高速率LDPC码的归一化MS算法和匹配行重量的MS算法,能够明显减少比较/选择运算次数。仿真表明,Nor-MS算法和Rwm-MS算法的性能与Log-BP算法性能很相近,但复杂度大大降低。可见,Nor-MS算法和Rwm-MS算法也是LDPC码解码的一种很好的可选方法。
In this paper, a variety of minimum and algorithm-related LDPC decoding algorithm and their parallel implementation of the verification node update typical hardware structure. For a check node update of a normalized MS, if the weight of the current row is dc, dc multiplication is needed, so if dc is large, it will inevitably lead to high complexity. A new verification node update method is proposed, which can significantly reduce the number of comparison / selection operations for the normalized MS algorithm of high-rate LDPC codes and the MS algorithm of line weight matching. Simulation shows that the performance of Nor-MS algorithm and Rwm-MS algorithm is similar to that of Log-BP algorithm, but the complexity is greatly reduced. It can be seen that the Nor-MS algorithm and the Rwm-MS algorithm are also good alternatives for LDPC code decoding.