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本文将论述一种具有4个选定芯片结构的选择数据I/O缓冲器和10MHz并联或50MHz串联数据转换的80ns256k金属栅DRAM。 采用具有25nm单元和32nm栅氧化的N沟二层金属栅工艺制造出了存贮器芯片(图1)。它是用
This article discusses a select data I / O buffer with four selected chip structures and 80ns256k metal gate DRAM with 10MHz parallel or 50MHz serial data conversion. A memory chip was fabricated using a N-channel two-layer metal gate process with 25 nm cell and 32 nm gate oxidation (FIG. 1). It is used