In this paper, a turbo iterative receiver structure with chip equalization is proposed for the 3G high-speed downlink packet access (HSDPA) systems. The receiver equalizes the channel prior to the dispreading and then performs two successive soft-output decisions, achieved by a soft-input soft-output (SISO) multi-code de- tector and a SISO turbo decoder through an iterative process. At each iteration, extrinsic information is extracted from detection and decoding stages and is then used as a priori information in the next iteration, just as in turbo decoding. Com- puter simulations show that the turbo iterative receiver structure with chip equali- zation offers significant performance gain over the traditional receiver structure. In this paper, a turbo iterative receiver structure with chip equalization is proposed for the 3G high-speed downlink packet access (HSDPA) systems. The receiver equalizes the channel prior to the dispreading and then performs two successive soft-output decisions, achieved by a soft-input soft-output (SISO) multi-code de-tector and a SISO turbo decoder through an iterative process. At each iteration, extrinsic information is extracted from detection and decoding stages and is then used as a priori information in the next iteration just as in turbo decoding. Com- puter simulations show that the turbo iterative receiver structure with chip equalization offers significant performance gain over the traditional receiver structure.