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衡量DSP(数字信号处理器)芯片性能的一个重要指标是单位时间内能够完成乘累加操作的数量。乘累加速度的增加就会使得DSP芯片运算速度增加。因此,通过对数据通路中的乘法器进行各种设计分析,得出适合32位浮点DSP结构的乘法器,为得到较优的乘累加设计奠定了基础。
An important metric for measuring the performance of a DSP (digital signal processor) chip is the number of multiply-accumulate operations per unit of time. By increasing the cumulative acceleration will make DSP chip computing speed increases. Therefore, through the design of the multiplier in the data path, we get the multiplier suitable for 32-bit floating-point DSP structure, which lays a good foundation for obtaining the multiply-accumulate design.