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提出了一种考虑工艺变化下快速时序优化的缓冲器插入方法,该方法在布线区域内对线网结构进行图变换,把随机问题变为确定性问题,也就是把工艺变化下缓冲器插入时序优化问题等效成统计最短路径问题;同时,在构建图的过程中提出一种有效节点存储算法,将有效节点个数从指数级降为平方级,大大提高了存储和运行的效率.针对90 nm、65 nm和45 nm工艺下全局互连线缓冲器插入对本方法进行分析和验证,插入结果与已有方法的结果一致,证明了本方法的有效性;将该方法应用于直线线网和树型线网这两类集成电路中实际的互连线网,在分别插入17个缓冲器和3个缓冲器下达到了最优时序优化结果.
A buffer insertion method is proposed which considers fast timing optimization under process variation. This method maps the network structure in the wiring area and turns the stochastic problem into a deterministic one. That is, the buffer insertion timing The optimization problem is equivalent to the statistic shortest path problem. At the same time, an effective node storage algorithm is proposed in the process of building the graph, which reduces the number of effective nodes from exponential to square, which greatly improves the efficiency of storage and operation. The results show that the proposed method is validated by inserting the global interconnection buffer in the process of nm, 65 nm and 45 nm. This method is proved to be effective. The method is applied to the linear net and The actual interconnect network in both types of ICs achieves optimal timing optimization results by inserting 17 buffers and 3 buffers respectively.