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文中以给出的一个状态机为例,然后用异步时序状态机的设计方法得到最终的电路,最后用Verilog语言描述其电路并在modelsim上进行逻辑测试,测试结果表明所设计的电路是正确的。
In this paper, a state machine is given as an example, and then the final circuit is obtained by the design of asynchronous sequential state machine. Finally, the circuit is described by Verilog and tested on modelsim. The test results show that the designed circuit is correct .