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A novel class-AB implementation of a current-mode programmable gain amplifier(CPGA) including a current-mode DC offset cancellation loop is presented. The proposed CPGA is based on a current amplifier and provides a current gain in a range of 40 d B with a 1 d B step. The CPGA is characterized by a wide range of current gain variation, a lower power dissipation, and a small chip size. The proposed circuit is fabricated using a 0.18 m CMOS technology. The CPGA draws a current of less than 2.52 m A from a 1.8 V supply while occupying an active area of 0.099 m2. The measured results show an overall gain variation from 10 to 50 d B with a gain error of less than 0.40 d B. The OP1 d Bvaries from 11.80 to 13.71 d Bm, and the 3 d B bandwidth varies from 22.2 to 34.7 MHz over the whole gain range.
A novel class-AB implementation of a current-mode programmable gain amplifier (CPGA) includes a current-mode DC offset cancellation loop presented. The proposed CPGA is based on a current amplifier and provides a current gain in a range of 40 d B The CPGA is characterized by a wide range of current gain variation, a lower power dissipation, and a small chip size. The proposed circuit is fabricated using a 0.18 m CMOS technology. The CPGA draws a current less than 2.52 m A from a 1.8 V supply while occupying an active area of 0.099 m2. The measured results show an overall gain variation from 10 to 50 d B with a gain error of less than 0.40 d B. The OP1 d Bvaries from 11.80 to 13.71 d Bm, and the 3 d B bandwidth varies from 22.2 to 34.7 MHz over the whole gain range.