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基于GF 130nm CMOS工艺,设计了一种低参考杂散、高电源噪声抑制比(PSNR)的Ⅰ型锁相环。相较于电荷泵型锁相环,Ⅰ型锁相环存在锁定范围小、参考杂散性能差等缺点。此外,压控振荡器是对电源噪声敏感的模拟电路,电源线上的噪声会恶化振荡器的输出抖动性能。通过引入采样保持电路和电源电压整形器,降低了Ⅰ型锁相环的参考杂散和电源噪声敏感系数。仿真结果表明,设计的I型锁相环的工作频率范围为2.1~2.8GHz,参考杂散为-66dBc,PSNR为-25dB,功耗为10mW,芯片占用面积为0.009mm2。
Based on the GF 130nm CMOS process, a type Ⅰ phase-locked loop with low reference spur and high power supply noise rejection ratio (PSNR) is designed. Compared with the charge pump type phase-locked loop, type I PLL has a small locking range, poor reference spurious performance and other shortcomings. In addition, the voltage-controlled oscillator is a power supply noise-sensitive analog circuit, the power line noise will deteriorate the oscillator output jitter performance. The introduction of sample-and-hold circuits and supply voltage shapers reduces Type I PLL reference spurs and supply noise sensitivity. The simulation results show that the design of the I-type PLL operating frequency range of 2.1 ~ 2.8GHz, the reference spurious -66dBc, PSNR -25dB, power consumption is 10mW, the chip footprint is 0.009mm2.