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室温下,沟槽底部有氧化物间隔的结势垒肖特基二极管的击穿电压达到2 009V,正向导通压降为2.5V,在正向偏压为5V时,正向电流密度为300A/cm2。在P型多晶硅掺杂的有源区生成双层SiO2间隔,以优化漂移区电场分布,正向导通压降为2.5V,击穿电压达到2 230V,耐压值提高11%。反向电压为1 000V时,反向漏电流密度比普通结构降低90%,有效地降低了器件的漏电功耗。普通结构的开/关电流比为2.56×103(1~500V),而改进结构的开/关电流比为3.59×104(1~500V)。
At room temperature, the breakdown voltage of the junction barrier Schottky diode with oxide spacing at the bottom of the trench reaches 2 009V with a forward conduction voltage drop of 2.5V and a forward current density of 300A at a forward bias of 5V / cm2. In the P-type polysilicon doped active region, a double-layer SiO2 spacer is generated to optimize the electric field distribution in the drift region. The forward voltage drop is 2.5V, the breakdown voltage reaches 2,230V, and the breakdown voltage increases by 11%. When the reverse voltage is 1 000V, the reverse leakage current density is reduced by 90% compared with the common structure, which effectively reduces the leakage power consumption of the device. The common structure has an on / off current ratio of 2.56 × 10 3 (1 to 500 V), while the improved structure has an on / off current ratio of 3.59 × 10 4 (1 to 500 V).