介绍一种ＳＤＨ 系统专用集成电路的设计，它可以从ＶＣ４ 信号中任意上下分插出多达２１ 个Ｅ１ 信号，包括Ｅ１ 的线路编解码及数字解同步器、码速调整及去调整、ＶＣ１２开销的终结及生成、ＴＵ１２ 的指针调整及解释、ＶＣ４ 的合成及分解。电路设计既充分考虑ＩＴＵ－Ｔ的标准，又结合实际系统设计，克服了以前电路的缺点，具有规模大、功能完善、性能优越的特点 This paper introduces a design of SDH system ASIC. It can divide up and down up to 21 E1 signals from any VC4 signal, including line codec and digital desynchronizer of E1, code speed adjustment and readjustment, VC12 overhead The end and generation, TU12 pointer adjustment and interpretation, VC4 synthesis and decomposition. The circuit design not only fully considers the standards of ITU-T, but also combines the actual system design to overcome the shortcomings of the previous circuits and has the characteristics of large scale, perfect functions and superior performance