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用混合电路布局方法使用npn和pnp晶体管设计了直流稳定随机存取存贮单元。就目前的制作容差,使用标准的双极工艺制作了2×3矩阵的试验单片。由于元件的合拼,一个单元所需面积只有14密耳~2。而且,单元能在低于每单元0.1微瓦的极低的直流待机功率下工作。尽管待机功率这样低,一个模拟的512位矩阵在脉冲功率下测得了10毫微秒的取数时间。
A DC stabilized random access memory cell was designed using hybrid circuit layout using npn and pnp transistors. For the current make tolerance, a test piece of 2 × 3 matrix was made using a standard bipolar process. Due to the combination of components, a unit required area of only 14 mils ~ 2. Moreover, the unit can operate at very low DC standby power of less than 0.1 microwatts per cell. Although the standby power is so low, an analog 512-bit matrix measures the fetch time of 10 nanoseconds at pulsed power.