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研究分栅快闪存储器弱擦除失效的机理,提出一种利用湿法刻蚀来调整浮栅侧墙氧化物的高度和宽度的工艺方法,该方法可以有效的调整浮栅尖端的高度和获得最优化的浮栅尖端形状,从而实现最优化字线与浮栅的耦合比率及增强擦除时浮栅尖端附近的电场的目的。通过对不同湿法刻蚀条件下晶片良率/耐久特性进行对比,我们发现减少40%湿法刻蚀时间的晶片具有更低的弱擦除失效率和更大的耐久性工作窗口。
In this paper, the mechanism of weak erase failure of split-gate flash memory is researched. A technique of wet etching to adjust the height and width of the floating gate oxide is proposed. The method can effectively adjust the height of the floating gate and obtain Optimized floating gate tip shape to achieve the goal of optimizing the coupling ratio of the word line to the floating gate and enhancing the electric field near the tip of the floating gate during erasing. By comparing the wafer yield / durability characteristics under different wet etch conditions, we found that wafers with a 40% wet etch time have lower operating window for lower erase failure rates and greater durability.