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设计了一个适用于 MPEG2 MP@ML 标准的视频解码器结构 ,用 VHDL 语言进行了系统级的仿真和综合。系统工作时钟频率 40 MHz。用标准图象测试序列进行了验证 ,给出了测试结果和有关参数 ,满足 MPEG2 MP@ML 视频解码的实时处理要求。
A video decoder structure suitable for the MPEG2 MP @ ML standard is designed and system-level simulation and synthesis are performed in VHDL. System working clock frequency 40 MHz. The standard image test sequence was used to verify the test results and related parameters to meet the MPEG2 MP @ ML video decoding real-time processing requirements.