The expandability of high demands for multimedia applications brings out more and more video standards for improving the coding and compression efficiency. As the most commonly used transform, Discrete cosine transform(DCT) achieves excellent energy compaction property and good compression efficiency. Hardware sharing is the mostly used efficient strategy to reduce the cost for video codec. Based on traditional matrix factorization, this paper makes three observations to direct the design of proposed hardware sharing architecture. The proposed architecture can be generally used to compute 8×8 DCT of AVS, H.264, VC-1 and HEVC in a low cost way, and can be used to decode Full-HD and WQXGA formate video sequences in real time. The design has been synthesized in 0.13μm technology. The synthesis results show that the proposed architecture achieves76.9% reduction in gate count, 85.6% decrease in power consumption and 35% improvement in operational speed in comparison with other existing designs. The expandability of high demands for multimedia applications brings more and more video standards for improving the coding and compression efficiency. As the most commonly used transform, Discrete cosine transform (DCT) achieves excellent energy compaction property and good compression efficiency. Hardware sharing is the Based on traditional matrix factorization, this paper makes three observations to direct the design of proposed hardware sharing architecture. The proposed architecture can be generally used to compute 8 × 8 DCT of AVS, H .264, VC-1 and HEVC in a low cost way, and can be used to decode Full-HD and WQXGA formate video sequences in real time. The design has been synthesized in 0.13 μm technology. The synthesis results show that the proposed architecture achieves76.9% reduction in gate count, 85.6% decrease in power consumption and 35% improvement in operational speed in comparison with other existing de signs.