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据日本《JEE》杂心1983年3月号报道,松下、日立和东芝公司宣布制成16兆位DRAM样机,在一块芯片上可集成约3400万只晶体管。 松下公司采用线宽0.5μm技术及开型位线方法,形成1.5×2.2μm的存储单元,以位线和字线相交处形成的沟道环绕之。为了实现这一结构,该公司在每256条实字线处采用赝字线用以消除耦合噪音,为有较高的密度,在每两条位线上排列一个读出放大器。它采用包括水溶性聚合物和γ射线步进机的4层保护膜。松下公司宣布了16兆字×1位和4兆字×4位结构的器件,这两种芯片的尺寸为5.4×17.38mm,存取时间为65毫微秒。
According to Japan’s “JEE” bizarre March 1983 reported that Matsushita, Hitachi and Toshiba announced a 16-megabit DRAM prototype, a chip can be integrated about 34 million transistors. Matsushita used a linewidth of 0.5μm technology and an open bit line method to form a 1.5 × 2.2μm memory cell surrounded by a channel formed by the intersection of a bit line and a word line. In order to achieve this structure, the company uses pseudo-word lines at every 256 real word lines to eliminate coupling noise. To have a higher density, a sense amplifier is arranged on every two bit lines. It uses a 4-layer protective film that includes a water-soluble polymer and a gamma-ray stepper. Matsushita announced 16-gigabit x 1-bit and 4-megapixel x 4-bit devices, both with a size of 5.4 x 17.38mm and a 65 nanosecond access time.