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基于SMIC 0.18μm 1P6M标准CMOS工艺,设计了一种2.5Gb/s LVDS接收器电路。仿真结果表明,所设计的LVDS电路参数符合LVDS标准,LVDS接收器的输出信号上升沿抖动约为0.76ps,有效版图面积约为(83×44)μm2,能应用于高速数据接口。
Based on the SMIC 0.18μm 1P6M standard CMOS process, a 2.5Gb / s LVDS receiver circuit is designed. The simulation results show that the designed LVDS circuit parameters accord with the LVDS standard. The LVDS receiver output signal jitter is about 0.76ps at the rising edge and the effective layout area is about (83 × 44) μm2, which can be used in high speed data interface.