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为提高系统集成度,降低硬件开销,研究利用FPGA实现看门狗电路的方法,从而去掉硬件看门狗电路。对硬件看门狗电路的工作过程进行分析,给出利用FPGA实现看门狗电路的方法:利用FPGA的系统时钟对单片机送出的喂狗信号进行监测,当单片机由于程序跑飞而进入死循环后,喂狗信号消失,FPGA判定单片机工作异常,自动产生一个脉冲信号复位单片机。实验证明,利用FPGA实现看门狗电路定时精度更高,在1KHz系统时钟FPGA系统中,定时精度可以达到1ms。
In order to improve the system integration and reduce the hardware overhead, we study how to realize the watchdog circuit by FPGA, so as to remove the hardware watchdog circuit. The working process of the hardware watchdog circuit is analyzed. The method of using the FPGA to realize the watchdog circuit is given. The system clock of the FPGA is used to monitor the feed dog signal sent by the microcontroller. When the microcontroller enters the dead loop due to the program running, , The dog signal disappears, FPGA determine the abnormal work of the microcontroller, automatically generate a pulse signal reset microcontroller. Experiments show that the use of FPGA to achieve higher watchdog timing accuracy in 1KHz system clock FPGA system, the timing accuracy can reach 1ms.