本文着重讨论了版图设计对ECL超高速四线接收器传输延迟的影响。通S_(19)A版与S_(19)B版的对比,发现在相同工艺条件下,仅仅由于恰当地缩小了电路中晶体管的平面几何尺寸,即可使t_(Pd)减小20％以上。这一分析为实践证实,所研制的线接收器其t_(Pd)的典型值达0.8ns,比美国莫托洛拉公司七十年代中期产品MC1692快0.3ns左右。 This article focuses on the layout design of ECL super high speed four-wire receiver transmission delay. Through the comparison of the S_ (19) A and S_ (19) B plates, it is found that under the same process conditions, the t Pd can be reduced by more than 20% merely by properly reducing the planar geometries of the transistors in the circuit. . This analysis confirmed that the developed line receiver has a typical value of 0.8 ns for t Pd, which is about 0.3 ns faster than the MC1692 product of the United States Motolora Company in the mid-1970s.