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本文在分析MOSFET衬底电流原理的基础上 ,提出了一种新型抗热载流子退化效应的CMOS数字电路结构 .即通过在受热载流子退化效应较严重的NMOSFET漏极串联一肖特基二级管 ,来减小其所受电应力 .经SPICE及电路可靠性模拟软件BERT2 .0对倒相器的模拟结果表明 :该结构使衬底电流降低约 5 0 % ,器件的热载流子退化效应明显改善而不会增加电路延迟 ;且该电路结构中肖特基二级管可在NMOSFET漏极直接制作肖特基金半接触来方便地实现 ,工艺简明可行又无须增加芯片面积 .
In this paper, based on the analysis of MOSFET substrate current principle, a new type of CMOS digital circuit structure with hot carrier degradation effect is proposed, that is, a Schottky barrier is connected in series with drain of NMOSFET, Diode to reduce the stress on the device.The simulation results of SPICE and circuit reliability simulation software BERT2.0 on the inverter show that the structure reduces the substrate current by about 50% The degeneration effect is obviously improved without increasing the circuit delay; and the Schottky diode in the circuit structure can be directly and conveniently made by directly fabricating the Schottky semi-contact in the drain of the NMOSFET, and the process is simple and feasible without increasing the chip area.