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存储器管理部件 MMU( memory managementunit)的速度直接影响微处理器的性能 ,提高存储器管理部件的速度是本文的设计目标。文中提出了存储器管理部件 MMU设计方法 ,论述了虚拟地址空间映射到物理地址空间逻辑关系 ,确定了 MMU是由暂存器、加法器、段测试电路、高速缓存器 CACHE和地址锁存器 latcher组成 ,给出了 MMU的数据通路和控制通路。经 EDA工具Synopsys仿真 ,结果显示传送于数据通路上的三种类型的操作数在控制流的作用下形成物理地址的时间是 1 .6个处理器周期 ,低于微处理器的最短存储器访问周期 ( 2 )
The speed of the memory management unit (MMU) directly affects the performance of the microprocessor. It is the goal of this article to improve the speed of the memory management unit. In this paper, the MMU design method of memory management unit is proposed. The logical relationship between virtual address space and physical address space is discussed. MMU is determined by register, adder, segment test circuit, cache CACHE and address latcher , Gives the MMU data path and control path. The EDA tool Synopsys simulation results show that the three types of operands transmitted in the data path under the control of the flow of physical address formed by the time is 1.6 processor cycles below the microprocessor’s shortest memory access cycle ( 2 )