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为一款支持802.11a/b/g协议的WLAN芯片设计了接收机内部的流水线A/D转换器。采用运放共享技术,减少了一半的运算放大器,节省了芯片面积,并降低了功耗。该A/D转换器采样速率为40 MHz,设计精度为10位,使用HJTC 0.18μm 1P6M CMOS工艺流片并测试成功,当输入频率为1 MHz、无杂散动态范围为61.43 dB的正弦信号时,测得输出数字信号的无杂散动态范围为58.6 dB,信号与噪声谐波失真比为52.87 dB,有效位数为8.49位。
Designed for a WLAN chip that supports 802.11a / b / g protocol, the receiver’s internal pipeline A / D converter. Using op amp sharing technology, it reduces the op amp by half, saves chip area and reduces power consumption. The A / D converter sampling rate of 40 MHz, the design accuracy of 10, the use of HJTC 0.18μm 1P6M CMOS process flow and successful test, when the input frequency of 1MHz, spurious-free dynamic range of 61.43dB sinusoidal signal The measured spurious-free dynamic range of the output digital signal is 58.6 dB, the signal-to-noise harmonic distortion ratio is 52.87 dB, and the effective number of bits is 8.49 bits.