在两相交叠CCD结构中,两个存储栅之间间隙的势垒高度由于边缘场效应,将随着间隙长度的减小而降低。在短沟道CCD中,势垒高度的降低会限制电荷处理能力。提出了一个两维模型来计算各种间隙长度下的势垒高度。阐述了一种简单的测量技术,采用亚微米结构以得到实验数据,并将该数据与模型进行了比较。考虑到设计需要,对几个与势垒降低有关的重要工艺参数进行了研究讨论。 In a two-phase overlapped CCD structure, the barrier height of the gap between the two memory gates will decrease as the gap length decreases due to the fringing field effect. In short-channel CCDs, lowering of the barrier height limits the charge handling capability. A two-dimensional model was proposed to calculate the barrier heights for various gap lengths. A simple measurement technique is described, using sub-micron structure to get the experimental data, and comparing the data with the model. Considering the design requirements, several important process parameters related to barrier reduction are discussed.