本文提出了一种基于FPGA的多路AES/E- BU数字音频采集监控系统的设计方案,该方案没有使用PLL(Phase Locked Loop锁相环)接收AES/EBU数字流,而是使用FPGA芯片接收AES/EBU信号。本文对其中的FPGA直接解码AES/EBU数据流、FPGA作为UART驱动数据输出两个关键技术进行了阐述。实验结果表明,在一块ALTERA cyclone 2c8 FPGA芯片设计并实现的32路AES数字音频采集系统不仅运行稳定,而且显著降低了系统成本。 This paper presents a FPGA-based multi-channel AES / E-BU digital audio capture monitoring system design, the program does not use PLL (Phase Locked Loop) to receive AES / EBU digital stream, but the use of FPGA chip to receive AES / EBU signal. In this paper, FPGA decoding AES / EBU data stream directly, FPGA as UART driven data output two key technologies are described. The experimental results show that the 32-channel AES digital audio acquisition system designed and implemented on an ALTERA cyclone 2c8 FPGA chip not only runs stably, but also significantly reduces the system cost.