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采用TSMC 0.18μm混合CMOS工艺,设计了一种应用在1.571GHz GNSS接收机中低杂散锁相环的鉴频鉴相器与电荷泵电路。鉴频鉴相器采用两相非重叠时钟结构和延时可控电路,实现了鉴频鉴相器的延时失配最小化和导通时间可调,在降低杂散的同时消除死区。电荷泵采用4路控制信号和1路可控充电和放电电路,有效地优化了电流失配和电荷泵电流的大小,进一步降低锁相环的杂散。测试结果表明,在电源电压为1.8V,电荷泵电流为100μA时,延时失配和充放电电流失配近似为0,杂散为-71.77dBc@16.375 MHz。
Using the TSMC 0.18μm hybrid CMOS technology, a phase-frequency detector and charge pump circuit for a low-spurious PLL in a 1.571GHz GNSS receiver is designed. The phase frequency detector adopts two-phase non-overlapping clock structure and delay controllable circuit to realize the minimum delay mismatch of the phase frequency detector and the adjustable on-time, and reduce the spurs while eliminating the dead zone. The charge pump uses four control signals and one controllable charge and discharge circuit, effectively optimizing the size of the current mismatch and charge pump current to further reduce the spurious of the phase-locked loop. The test results show that the delay mismatch and the charge-discharge mismatch are approximately zero with the supply voltage of 1.8V and the charge pump current of 100μA, and the spurious is -71.77dBc@16.375MHz.