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本文总结了n阱CMOS工艺的优点.工艺设计的主要考虑是从VLSI观点出发以达到高性能、高速度和高密度并与NMOS工艺相容.应用全离子注入技术、局部氧化方法、n~+掺杂且不含硼杂质的多晶硅栅、等离子体腐蚀以及70nm的薄栅氧化层,制成4μm沟道长度的CMOS电路.通过进一步改进光刻技术,本工艺可用于制造微米级或亚微米级短沟道器件.制作的器件参数和用SUPREMⅡ程序分析和模拟的结果符合得很好.若增加一块制作耗尽型n沟MOS晶体管的掩模版,本工艺也可很容易地扩展成N-MOS/CMOS工艺.
This article summarizes the advantages of n-well CMOS technology, the main consideration of process design is to achieve high performance, high speed and high density from the VLSI point of view and to be compatible with the NMOS process. All-ion implantation, Doped polysilicon gate without boron impurities, plasma etching and a thin gate oxide of 70 nm to form a CMOS circuit with a channel length of 4 [mu] m By further improving the lithographic technique, the present process can be used to fabricate micron or submicron Short-channel devices. The fabricated device parameters are in good agreement with the results of the SUPREM II program analysis and simulation. The process can also be easily extended to N-MOS if one is added to create a reticle of a depletion n-channel MOS transistor / CMOS process.