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现场可编程门阵列(FPGA)已经不再单纯应用在芯片与系统之间的直接互联层,在软件无线电(SDR)中,FPGA逐渐用做通用运算架构来实现硬件加速单元,在降低成本和功耗的基础上提升性能表现。SDR调制解调器的典型实现包括通用处理器(GPP)、数字信号处理器(DSP)和FPGA。而且,FPGA架构可以结合专用硬件加速单元,用来卸载GPP或DSP。软核微处理器可以结合定制逻辑,扩展其内核,也可以将分立的硬件加速协处理器添加到系统中。此外,还可将通用布线资源放在FPGA中,这些硬件加速单元可以并行运行,进一步增强系统的整体运算输出能力。本文将讨论三种不同类型的硬件加速单元,以及它们通过软件实现的性能。
Field programmable gate arrays (FPGAs) are no longer simply applied to the direct interconnect layer between the chip and the system. In software radio (SDR), FPGAs are increasingly used as general purpose computing architectures to implement hardware acceleration units, reducing cost and effort Consumption based on improving performance. Typical implementations of SDR modems include general purpose processors (GPPs), digital signal processors (DSPs), and FPGAs. Moreover, the FPGA fabric can be combined with a dedicated hardware acceleration unit to offload GPP or DSP. Soft-core microprocessors can be combined with custom logic to extend their cores, or add discrete hardware-accelerated coprocessors to the system. In addition, the common routing resources can also be placed in the FPGA, these hardware acceleration units can be run in parallel, to further enhance the overall operational output of the system. This article will discuss three different types of hardware acceleration units and their performance in software.