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在10厘米长2厘米宽的YZ LiNbO_3基片上用四个多带反射轨迹变换器把45厘米长的延迟通道折叠成五条相邻的轨迹。在带宽15兆赫(受换能器限制)、总调谐损耗23分贝下、中心频率74兆赫时总的信号延迟130微秒。整个结构都采用标准光刻由一个掩模复印在平面抛光基片的一面。本文介绍在单个轨迹变换器设计中的重要改进。例如切比捷夫(Chebycheff)指条长度加权可以降低各耦合器端面反射回来的假信号,但4个轨迹变换器的典型的17条断指的任意反射点会使主要的假信号只比主信号低30分贝。延时达500微秒和带宽大于50兆赫的延迟线采用这种技术是有可能实现的。
Four 45-nm long delay channels were folded into five adjacent tracks on a 10 cm long and 2 cm wide YZ LiNbO_3 substrate using four multi-band reflective locus transducers. With a bandwidth of 15 megahertz (limited by the transducer), the total tuning loss is 23 decibels and the total signal delay is 130 microseconds at a center frequency of 74 MHz. The entire structure is prepared using standard lithography by a mask on one side of a flat polished substrate. This article describes important improvements in the design of a single track converter. For example, the Chebycheff strip length weighting can reduce the glitch reflected from the coupler end faces, but the arbitrary reflection point of a typical 17 fingers of the 4 track transformers will cause the dominant glitch to be only slightly larger than the main signal Low 30 dB. Delay lines up to 500 microseconds and bandwidths greater than 50 MHz are possible with this technique.