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介绍了一种适合于高速模数转换器(ADCs)的预放大-锁存(preamplifier-latch)CMOS比较器。此电路结构包括一个预放大器、锁存比较器和输出缓冲器。在预放大器和正反馈锁存比较器之间加入分离电路,以此来减少回扫(kickback)噪声对电路的影响。采用0.35μm标准CMOS工艺库,在Cadence环境下进行仿真,该比较器在时钟频率为500 MHz,采样频率为40 MHz的时候,可以达到30μV的精度,功耗大约为0.6 mW。
A preamplifier-latch CMOS comparator suitable for high speed analog-to-digital converters (ADCs) is introduced. This circuit structure includes a pre-amplifier, latch comparator and output buffer. The separation circuit is added between the preamplifier and the positive feedback latch comparator to reduce the effects of kickback noise on the circuit. The 0.35μm standard CMOS technology library is used to simulate a Cadence environment. The comparator achieves an accuracy of 30μV at a clock frequency of 500 MHz and a sampling frequency of 40 MHz, with a power dissipation of approximately 0.6 mW.