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概论目前大规模集成的发展趋势,给设计毫微秒数字逻辑系统带来新的限制。特别是,随着集成度的提高,要求用比以前较低的功耗实现更复杂的逻辑功能,而又要保持高密度装配的快速优点,就更是如此。组件连接的数目,图形的复杂性和扇出、扇入能力,对电路和逻辑设计者提出了其他限制。有人建议,两级逻辑结构可以满足上面的要求并且如果逻辑输入变量按照其到达的时间划分,就可以获得最大速度。本文简述多射极两级逻辑电路(METLL)的工作原理,并且提出单输出两级组合网络的逻辑划分方法。通过某些具体的例子,说明算法的应用。这些例子是全加器以及迭代乘法器。
Overview The current trend of large-scale integration, to the design of nanosecond digital logic system to bring new restrictions. In particular, this is all the more true as integration increases require the implementation of more complex logic functions at lower power consumption than before, while maintaining the rapid benefits of high-density assembly. The number of component connections, the complexity of the graphics, and the fan-out, fan-in capability place other constraints on the circuit and logic designers. It has been suggested that two-level logic structures satisfy the above requirements and that the maximum speed is obtained if the logical input variables are divided by the time of their arrival. This article briefly describes the working principle of the multi-emitter two-stage logic circuit (METLL), and proposes the logic division method of single output two-stage combined network. Through some specific examples, illustrate the application of the algorithm. These examples are full adders and iterative multipliers.