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本文给出了一个面积优化、低复杂度、具有8位纠错能力的Reed-Solomon(63,47)编解码芯片的VLSI实现。此芯片将用于CDPD(CellularDigitalPacketData)通信系统犤1犦。由于Euclid算法规则、简单,很自然地适合VLSI实现,因此本文采用Euclid算法实现RS解码部分。在编码部分里,又采用了基于特定复合域的常数乘法器,它极大的降低了编码器的面积。同时基于复合域GF((2n)2)的乘法器的采用极大地降低了RS解码器的乘法复杂度。此RS编解码芯片能独立的工作在15MHz。芯片采用0.6um1P2MCMOS5v电压的工艺进行制造。芯片最终裸片面积是4mmx4mm。芯片成功经过测试并满足CDPD通讯系统的要求。
This paper presents a VLSI implementation of Reed-Solomon (63,47) codec with optimized area, low complexity and 8-bit error correction. This chip will be used in CDPD (CellularDigitalPacketData) communication system 犤 1 犦. Because Euclid algorithm rules, simple and naturally suitable for VLSI implementation, this paper uses the Euclid algorithm RS decoding part. In the coding part, a constant multiplier based on a specific compound domain is adopted, which greatly reduces the area of the encoder. At the same time, the adoption of the multiplier based on the composite domain GF ((2n) 2) greatly reduces the multiplication complexity of the RS decoder. This RS codec chip can work independently at 15MHz. Chip 0.6um1P2MCMOS5v voltage of the manufacturing process. The die’s final die area is 4mmx4mm. The chip has been successfully tested to meet the requirements of the CDPD communications system.