一、问题的由来脉冲吞除是在研制单环数字式频率合成器的高速程序分频时提出来的.单环数字式频率合成器的方框图如图1所示.它的主要特点是在锁相环路中插入一个分频比可变的程序计数器,利用改变分频比以改变压控振荡器VCO的输出频率.分频后的信号与基准信号在鉴相器中比相,得出误差电压去控制VCO的频率.由此得到大量稳定的工作频率.程序计数器通常由多级分频比可变的十进计数器和一些附加电路组成,如图2所示.它每完成一个计 First, the origin of the problem Pulse swallow is in the development of single-loop digital frequency synthesizer high-speed program frequency is presented when the single ring digital frequency synthesizer block diagram shown in Figure 1. Its main feature is the lock Phase loop insert a variable frequency divider program counter, the use of changes in the frequency divider to change the VCO VCO output frequency divided by the signal and the reference signal in the phase detector phase, resulting in error Voltage to control the VCO frequency, which results in a large number of stable operating frequency Program counter is usually multi-stage variable frequency divider counter and a number of additional circuits, as shown in Figure 2. Each of its completion of a meter