论文部分内容阅读
提出并实现了一种基于Verilog模拟器与C模拟器协同模拟的微处理器验证平台Bug Finder.该平台通过System Verilog DPI(Direct Programming Interface)和操作系统共享内存机制,将待验证微处理器的RTL模型与GEM5模拟器相连,并自动比较每条指令的运行结果,可以发现深层次的设计错误并快速定位.在实际验证中的应用结果显示,Bug Finder平台可以快速定位到大量RTL设计和验证环境中的错误,有效缩短了处理器的验证周期.
This paper proposes and implements a microprocessor verification platform based on Verilog simulator and C simulator to simulate the bug finder. The system integrates the memory mechanism through the System Verilog DPI (Direct Programming Interface) and the operating system, The RTL model is connected to the GEM5 simulator and automatically compares the results of each instruction to find deep-level design errors and locate quickly. The practical validation results show that the Bug Finder platform can quickly locate a large number of RTL designs and verifications Errors in the environment effectively shorten the processor’s verification cycle.