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采用5+7的分段方式,设计了一种12位1GHz电流舵数模转换器(DAC),分析了电流源版图误差对DAC性能的影响。为了抵消DAC版图的梯度失配误差,提出一种新型随机增减动态元件匹配(DEM)算法,并将其加入到高5位温度计码中,以优化DAC的动态性能。基于TSMC0.18μm CMOS工艺,完成了整个DAC的电路设计,并与常规DEM算法进行仿真比较,结果显示,在输入数据频率分别为10MHz和120MHz时,该DAC的无杂散动态范围(SFDR)分别提升7.2dB和3.8dB。
A 5-to-7 segmented approach was used to design a 12-bit, 1-GHz, current-stepping digital-to-analog converter (DAC) that analyzed the effect of current source layout errors on DAC performance. In order to counteract the gradient mismatch error of the DAC layout, a novel random-add-drop dynamic element matching (DEM) algorithm is proposed and added to the upper 5-bit thermometer code to optimize the dynamic performance of the DAC. Based on the TSMC 0.18μm CMOS process, the circuit design of the entire DAC is completed and compared with the conventional DEM algorithm. The results show that the spurious-free dynamic range (SFDR) of the DAC is 10MHz and 120MHz, respectively Boost 7.2dB and 3.8dB.