介绍140万像素、每秒7.5帧高清高速数字摄像机的电路设计方案。该设计主要由SONY的CCD ICX205AK,Analog Devices模拟前端电路AD9923A以及Xilinx的FPGA XC3S1200E,TOKYO的JPEG压缩芯片TE3310RPF和ATMEL的ARM芯片AT91RM9200等组成。模拟前端电路AD9923A实现CCD水平和垂直时序的产生,CCD的放大,CCD信号的模数转换三大功能;CCD ICX205AK输出信号经模拟前端电路AD9923A进行放大和模数变换后,输入到FPGA进行数据格式处理,生成YUV信号输入到压缩芯片进行JPEG压缩,然后由ARM通过网络将压缩数据传送到客户端。实验结果表明,该设计方案每秒可以采集、压缩、传输140万像素图像7.5帧。 Introduced 1.4 million pixels, 7.5 frames per second high-speed high-speed digital camera circuit design. The design is mainly composed of SONY CCD ICX205AK, Analog Devices analog front-end circuit AD9923A and Xilinx FPGA XC3S1200E, TOKYO’s JPEG compression chip TE3310RPF and ATMEL’s ARM chip AT91RM9200 and other components. Analog front-end circuit AD9923A CCD horizontal and vertical timing generation, CCD amplification, CCD signal analog-digital conversion three functions; CCD ICX205AK output signal through the analog front-end AD9923A amplification and analog-to-digital conversion, the input to the FPGA for data format Processing, generate YUV signal input to the compression chip for JPEG compression, and then by ARM through the network to send compressed data to the client. Experimental results show that the design can capture, compress and transmit 1.4 megapixel images per second.