论文部分内容阅读
本作品以FPGA和单片机为核心控制器件,由前置放大模块、带阻网络模块、A/D采样模块、FPGA采样控制及存储模块、FPGA的FFT和IFFT计算模块、幅值均衡模块、D/A时钟控制模块等组成。系统的前置放大器电压增益达到56dB,带阻网络相对于10kHz时的输出幅值最大衰减可达-13.6dB,经过数字幅频处理之后,以10kHz时的输出幅值为基准,通频带20Hz～20kHz内的电压幅值波动在以内。系统在输入电压为5mVrms时,功率放大电路的输出功率可达12.75W,并且功率放大电路的效率可达71.6%,系统输出信号无明显失真。经过实际测试,系统各项指标达到了题目的设计要求。
This work regards FPGA and one-chip computer as the core control device, consists of preamplifier module, band blocking network module, A / D sampling module, FPGA sampling control and storage module, FPGA FFT and IFFT calculation module, amplitude equalization module, D / A clock control module and other components. System preamplifier voltage gain up to 56dB, band-stop network relative to the maximum output amplitude of 10kHz attenuation up to -13.6dB, after the digital amplitude-frequency processing, the output amplitude at 10kHz as a benchmark, passband 20Hz ~ Voltage fluctuations within 20kHz are within. When the input voltage is 5mVrms, the output power of the power amplification circuit can reach 12.75W, and the efficiency of the power amplification circuit can reach 71.6%. The system output signal has no obvious distortion. After the actual test, the system indicators reached the title of the design requirements.