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设计实现了一种超高速数据采集系统。通过在FPGA(现场可编程门阵列上)采用8个不同相位的时钟进行移相合成采集,采用一颗125MSPS采样率的ADC芯片成功实现了1GSPS采样率的高速采样。同时通过对采样数据进行累加求平均的滤波运算,有效地消除了背景噪声,提高了采样的精度。为了实现大数据量的采集,采用了DDR2作为存储器,其具有容量大,速度快,成本低的特点。FPGA采用Xilinx的Spartan6系列,内置了DDR2接口控制器,大大简化了设计。设计的高速数据采集系统在ISE软件中进行了综合,并在FPGA板上进行了实测,性能良好,实现了系统需求的各个指标。
Design and implementation of a high-speed data acquisition system. By using eight clocks with different phases on the FPGA (Field Programmable Gate Array) for phase-shift synthesis acquisition, a 1-MSPS sampling rate high-speed sampling was successfully achieved using a 125MSPS sampling rate ADC chip. At the same time through the sampling data accumulated and averaged filtering operation, effectively eliminating the background noise and improve the sampling accuracy. In order to achieve the acquisition of large amounts of data, the use of DDR2 as a memory, which has the capacity, speed, low cost. FPGA using Xilinx’s Spartan6 series, built-in DDR2 interface controller, greatly simplifying the design. The designed high-speed data acquisition system is integrated in the ISE software and measured on the FPGA board. The performance is good and various indexes of system requirements are realized.