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计数器电路是数字系统中使用最多的时序电路之一,不仅能用于对时钟脉冲计数,还可用于分频、定时、产生节拍脉冲和脉冲序列以及进行数字运算等。模可变计数器由于计数容量可以根据需要进行变化,为其广泛使用创造了便利。本论文基于复杂可编程逻辑器件CPLD,在Altera QuartusⅡ开发环境下,用Verilog HDL语言设计了一种具有清零、置数、使能控制、可逆计数和具有模可变功能的计数器。
The counter circuit is one of the most frequently used timing circuits in digital systems and can be used not only to count clock pulses, but also to divide, clock, generate beat pulses and pulse sequences, and perform digital operations. Modular variable counter due to the counting capacity can be changed as needed, creating convenience for its widespread use. Based on the CPLD of complex programmable logic device, this thesis designs a counter with clear function, set number, enable control, reversible counting and modulo function in Verilog HDL language in Altera Quartus II development environment.