A layout and connection optimiza-tion for static frequency divider is presented. The layout optimization provides a new circle topology transistors placement and reasonable connection structure, which reduces the par-asitic effectively and enables self-oscillation frequency enhancement. Besides, bandwidth enhancement techniques based on a center-tap capacitor in input balun design and inductive peaking in latch design are adopted to improve further high frequency performance with low power consumption. As a proof of concept, design of a divide-by-2 static frequency di-vider in 0.13 μm SiGe BiCMOS technology is reported. With single-ended input clock signal, the divider is measured to be operated from 40 to 90 GHz. Phase noise measurements of a 90 GHz input clock signal indicate ideal behavior with no measurable noise contribution from the divider. The divider followed by a buffer that can deliver more than -10 dBm output power, which is sufficient to drive succeeding stage. To the author’s knowledge, the divider exhibits a competitive power dissipation and the highest FOM among silicon based fre-quency dividers that operating higher than 70 GHz.