The effect of nitric oxide(NO) annealing on charge traps in the oxide insulator and transition layer in n-type4H–Si C metal–oxide–semiconductor(MOS) devices has been investigated using the time-dependent bias stress(TDBS),capacitance–voltage(C–V),and secondary ion mass spectroscopy(SIMS).It is revealed that two main categories of charge traps,near interface oxide traps(Nniot) and oxide traps(Not),have different responses to the TDBS and C–V characteristics in NO-annealed and Ar-annealed samples.The Nniotare mainly responsible for the hysteresis occurring in the bidirectional C–V characteristics,which are very close to the semiconductor interface and can readily exchange charges with the inner semiconductor.However,Not is mainly responsible for the TDBS induced C–V shifts.Electrons tunneling into the Not are hardly released quickly when suffering TDBS,resulting in the problem of the threshold voltage stability.Compared with the Ar-annealed sample,Nniotcan be significantly suppressed by the NO annealing,but there is little improvement of Not.SIMS results demonstrate that the Nniotare distributed within the transition layer,which correlated with the existence of the excess silicon.During the NO annealing process,the excess Si atoms incorporate into nitrogen in the transition layer,allowing better relaxation of the interface strain and effectively reducing the width of the transition layer and the density of Nniot. The effect of nitric oxide (NO) annealing on charge traps in the oxide insulator and transition layer in n-type 4 H-Si C metal-oxide-semiconductor (MOS) devices has been investigated using time-dependent bias stress -voltage (C-V), and secondary ion mass spectroscopy (SIMS) .It is revealed that both main categories of charge traps, near interface oxide traps (Nniot) and oxide traps (Not), have different responses to the TDBS and C -V characteristics in NO-annealed and Ar-annealed samples. Nilotare mainly responsible for the hysteresis occurring in the bidirectional C-V characteristics, which are very close to the semiconductor interface and can be readily exchanged charges with the inner semiconductor. is mainly responsible for the TDBS induced C-V shifts. Electrons tunneling into the Not are released quickly when when suffering TDBS, resulting in the problem of the threshold voltage stability. Compared with the Ar-annealed sample, Nniotcan be significantl y suppressed by the NO annealing, but there is little improvement of Not.SIMS results demonstrate that the Nniotare distributed within the transition layer, which correlated with the existence of the excess silicon. During the NO annealing process, the excess Si atoms incorporation into nitrogen in the transition layer, allowing better relaxation of the interface strain and effectively reducing the width of the transition layer and the density of nniot.